-
without then tool mistakenly reads from feedback signal like a register and is just wire connected to self connected to nothing...
```c
uint8_t reg_wr_data;
#pragma FEEDBACK reg_wr_data
if(t…
-
Ref. version 3.0.0, I have found that the tags list for VHDL are not complete. As a result, the results returned by the ctags invocation are very poor. I offer the following change to address this. No…
-
There are quite a few Ethernet MAC cores, but mostly in Verilog. I've a project written in VHDL, use GHDL, and therefore looked for a core written in VHDL, and found this project.
The core was tested…
wfjm updated
4 months ago
-
#### Feature request description
Currently Sourcegraph doesn't support syntax highlighting for Verilog and VHDL.
 of std_logic_vector(7 downto 0);
type t2 is array (natural range) of std_logic_vector(3 downto 0);
function foo
generic (type t)
parameter (si…
-
Hi,
I have hit the following issue with Signals with a set value (like `lsr = Signal(intbv(0x2eb1edd0, _nrbits=30))`. If, on conversion to VHDL, I use the parameter `initial_values=True` it generat…
-
Verification environment : CoCoTb + ghdl
OS : Ubuntu 24.04
I have specified , with json, and generated a simple set of registers being:
0x00 : RevId, RO
0x04 : Scratch, RW
```
{
…
-
- [x] vhdl-tools by Cayetano Santos [https://gitlab.com/emacs-elisp/vhdl-tools](https://gitlab.com/emacs-elisp/vhdl-tools)
- [ ] vhdl-capf [https://github.com/sh-ow/vhdl-capf](https://github.com/sh-…
-
ERROR: [XSIM 43-4187] File "C:/Users/NALLURI SASI KIRAN/Desktop/microwatt-master/wishbone_arbiter.vhdl" Line 41 : The "Vhdl 2008 Sequential Conditional Signal Assignment" is not supported yet for simu…
-
Dear,
is there already support for VHDL design entry via GHDL Yosys plugin ?
Hoping to receive a positive reaction, I remain,
Greetings,
Patrick Pelgrims