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Hi, I am working on the hello world test of "lowrisc-chip". The branch that I am working on is kc705_update. The problem is that I can generate the bitstream file and combine it with the "hello world"…
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Hi, expert:
Is it possibel to support xilinx kc705 or kcu105 board?
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I'm running Mint Linux 19.2, and I used the apt get method to install the fpgamake software on my machine.
One of the first steps I am trying is to build an example project, but I'm not able to, it s…
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I have a project that requires a Linux-compatible SoC to control and stream data from a hardware-implement neural network (NN). The NN uses the AXI bus interface so I need to add a Wishbone2AXI interf…
8pins updated
2 years ago
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Is KC705 full duplex? Because the light of the duplex of my development board is on
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On KC705, the link is able to initialize up to the U0 state, but the link is re-trained soon after. Understand why is causing this and verify that the link can stay in U0 state.
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Hi. I'm newbie on these tasks.
I wants to port picorv32 on my fpga board. (KC705 or ZCU102)
I tried to find various guides, but it was hard to find.
which looks better to port picorv32 using …
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I would like to use IPBus on a Digilent Genesys2 evaluation board. It uses the same FPGA as the KC705 but would require an RGMII interface to the PHY. I can see that each of these is used by different…
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This is a 3x3 system with the memory tile in the center of the system:
```
CT CT CT
CT MT CT
CT CT CT
```
Beside Verilator simulation it should be ported to the KC705 platform.
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WRPLL on Si549 is finally making some good progress, and it sounds like we are not going to need the Si5324 in the future.
Si5324 will remain supported in ARTIQ for legacy hardware and for the KC705/…