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cambridgehackers
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fpgamake
Generates Makefiles to synthesize, place, and route verilog using Vivado
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Example project misses 'bsc' command
#22
ranzbak
opened
4 years ago
1
how to install BSV compiler
#21
jangtsekiang
closed
5 years ago
2
Add support for unmanaged implementation constraint files
#20
acw1251
closed
5 years ago
1
Added hierarchical flag for report_utilization
#19
acw1251
closed
7 years ago
0
FPGA program not done due to DCI matching failure
#18
chanwooc
closed
8 years ago
1
floorplan in altera
#17
hanw
closed
8 years ago
0
build a module hierarchy graph, since netlist partition needs a full path.
#16
hanw
closed
8 years ago
0
netlist generation for altera
#15
hanw
closed
8 years ago
1
added script to generate from altera qsys
#14
hanw
closed
8 years ago
1
quartus flow fixes.
#13
hanw
closed
9 years ago
1
Add file path checker to flow (feature request)
#12
aolofsson
closed
9 years ago
3
README file needs updating
#11
aolofsson
closed
9 years ago
1
fpgamake dependancies
#10
aolofsson
closed
9 years ago
2
Support "-f" source file specification like verilator and icarus
#9
aolofsson
opened
9 years ago
2
support qmegawiz and stratix IV
#8
hanw
closed
9 years ago
0
Add SDC_FILE option and parameter for ip core generation.
#7
hanw
closed
9 years ago
0
catch compilation errors
#6
hanw
closed
9 years ago
0
removed the option --qsf from fpgamake
#5
hanw
closed
9 years ago
0
added support for altera signalscope II
#4
hanw
closed
9 years ago
0
Added altera generate ip_core function
#3
hanw
closed
9 years ago
1
Support Altera Quartus II IP file (.qip)
#2
hanw
closed
9 years ago
0
Add preliminary support for Altera FPGAs
#1
hanw
closed
9 years ago
1