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**Type of issue**: bug report
**Impact**: API modification
**Development Phase**: request
**Other information**
When running
litex-boards/litex_boards/targets/sipeed_tang_primer_20k.p…
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I need help with what appears to be a bug somewhere in the Amaranth/Yosys/Apicula ecosystem. It could also be me because this is my very first day playing around with Amaranth, Yosys, and Apicula. An…
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Currently the nextpnr BBA generation code includes a lot of duplication, particularly where lists are concerned. e.g. patterns like https://github.com/SymbiFlow/python-fpga-interchange/blob/6a80233ca…
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I have followed below link to download tool on ubuntu 16.04.
http://www.clifford.at/icestorm/
Where I am facing issue while installing nextpnr as below.
$ cmake -DARCH=ice40 -DCMAKE_INSTALL_PRE…
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## Issue Description
`memory_libmap` pass in Yosys 0.18 and newer would synthesize LUTRAMs unsupported by nextpnr including:
- RAMS32 (manually instantiated)
- RAMD32 (manually instantiated)
- R…
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nextpnr saves errors to `output/dir/nextpnr.err` but these aren't visible from `cargo run` command
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After waiting a few days without a response from Lattice for a free license, I decided to move forward without Icecube2 (Linux is more convenient for me, anyway!)
I've installed icestorm and the re…
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devel@pi5-70:~/pico-ice/my-new-pico-ice-firmware/ice_makefile_verilator_counter $ make
/usr/local//bin/yosys -q -p "read_verilog -sv ice40.sv top.sv; synth_ice40 -top ice40 -json gateware.json"
Warn…
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```
ctx.addClock("clk_out_a", 100)
ctx.addClock("clk_out_b", 12)
```
```
nextpnr-ice40 --pre-pack clocks.py
```
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The CI fails to build `nexpnr-xilinx`: https://github.com/hdl/conda-eda/runs/5446064939?check_suite_focus=true#step:4:1613
```
+ pypy3 xilinx/python/bbaexport.py --device xc7a35tcsg324-1 --bba /ho…