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The command to generate floating point assembly tests in the fadd.d_b1-01.S file[https://github.com/riscv-non-isa/riscv-arch-test/blob/main/riscv-test-suite/rv32i_m/D/src/fadd.d_b1-01.S](https://githu…
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The command to generate floating point assembly tests in the fadd.d_b1-01.S file[https://github.com/riscv-non-isa/riscv-arch-test/blob/main/riscv-test-suite/rv32i_m/D/src/fadd.d_b1-01.S](https://githu…
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Looking at the lastest GitHub released spec, under "Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`" there is this text:
```
The assembly syntax adds two mandatory flags to the `vsetvl…
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I faced this error while trying to add new instruction. The instruction will follow the same format of fmadd.
{"mod.s", 0, INSN_CLASS_F_INX, "D,S,T,R", MATCH_MOD_S|MASK_RM, MASK_MOD_S|MASK_…
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The assembly handling is currently tied to the riscv architecture, but most of the code is generic enough so that it can be extracted into an isolated assembly module.
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I am using the following command to generate arithmetic tests for `rv32i` target
```shell
python3 run.py --target rv32i -o $HOME/temporary/riscv-dv -tn riscv_arithmetic_basic_test -i 10 -si pyflow…
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When I write assembly code and C code for the same functionality that are simulated by spike, it turns out that assembly code can access MMIO device address but C code cannot. The source code is at ht…
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When I compiled pulp-platform/llvm-project and pulp-platform/pulp-riscv-gnu-toolchain. I want to compile the .s file to view the assembly representation of the hardware cycle. The error message shows:…
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I am trying to run the RISCV test on esesc. Specifically, dhrystone.
I cloned the riscv tests from: [](https://github.com/riscv/riscv-tests).
Then I built the binaries. The resulting dhyrstone.ri…
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Right now we are using Coq as a very weak assembler, and we have no convenient way of e.g. computing labels or offsets.
Links for inspiration (to expand):
- "Coq: the world's best macro assembler?…