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需求：
1. 在 [LLVM24.09_mugen失败测试用例清单](https://docs.qq.com/sheet/DSnFpcEJyVnJYRGJ1?tab=BB08J2) 中找到测试套 tpm-tools 失败的测试用例
2. 在 [openEuler LLVM 平行宇宙 24.09 版本](https://repo.tarsier-infra.isrc.ac.cn/openEu…
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Sail currently sets bits C, D, E, F, M, V and X in `misa`. This is wrong as D (double float), F (float) and V (vector) are not supported. ~~Also B (bit vector) is supported and should be set~~ (remove…
rmn30 updated
4 months ago
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./riscv_em -f fw_payload.bin -d riscv_em.dtb
or
./riscv_em -f fw_payload.bin -d riscv_em.dtb -i myfilesys.img // ext3
Both have the same error and hang there forever!
Please ad…
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I'm running pre-compiled elf files within the SAIL environment running under the C emulator.
There is a variable declared in c_emulator/riscv_platform_impl.c called rv_htif_tohost, which appears to …
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目前v0.3版本的 ruyi list 查询结果如下：
ruyi list
List of available packages:
* board-image/buildroot-sdk-milkv-duo-python
- 1.0.7 (latest)
* board-image/uboot-oerv-sipeed-lpi4a-16g
- 0.2309.1 (late…
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Hi,
everything is running smoothly until I try to do `make run-emulator-debug`. That results in the following:
```
running basedir/Makefile: make run-emulator-debug
make -C emulator/rv32_1sta…
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### Technical Group
Applications & Tools HC
### ratification-pkg
Technical Debt
### Technical Liaison
Bill McSpadden
### Task Category
Sail
### Task Sub Category
- [ ] gcc
…
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**Impact**: simulator
**Tell us about your environment:**
*Chipyard Version:* 1.4.0, Hash 58076c
*OS:* Linux ubuntu 5.8.0-40-generic #45~20.04.1-Ubuntu SMP Fri Jan 15 11:35:04 UTC 2021 x86_64 x…
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hello
tried to simulate vexriscv
followed the instructions from Linux.scala
the linux files are
VexRiscvRegressionData/sim/linux
laur@laurPC-100:~/lucru/cn/riscv/vexriscv-linux/VexRiscv/src…
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https://github.com/rems-project/sail-riscv/blob/ae6cb1de092e9ea727e2318d76e9b88999bbee59/c_emulator/riscv_platform_impl.c#L15
E.g., for m mode, the physical address is not start from 0x80000000, or…