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This project seeks a set of Ghidra import regression tests to validate sensible behavior after importing executable binaries into new versions of Ghidra. It's morphed somewhat into generating newer e…
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First trial of refactoring, the [wasm branch](https://github.com/ChinYikMing/rv32emu/tree/wasm)'s latest commit is the result.
Since `state_t` is a user-provided data, so all runtime defined value…
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When I run make reports after 'make run-emulator' I get errors like these grep CPI emulator/rv32_1stage/output/_.out
make: [rv32_1stage-report-cpi] Error 1 (ignored)
and test-results.xml is all 0
$ ma…
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I followed this link https://github.com/kvm-riscv/howto/wiki/KVM-RISCV64-on-QEMU to start a emulated riscv host, but it failed with "sbi_hsm_hart_start_finish: ERR: The hart is in invalid state [21477…
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### Describe the project you are working on
V-Sekai is a self-hostable MIT open source software stack built with Godot Engine 4. This project aims to provide a robust and flexible platform for game…
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Hi,
everything is running smoothly until I try to do `make run-emulator-debug`. That results in the following:
```
running basedir/Makefile: make run-emulator-debug
make -C emulator/rv32_1sta…
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https://github.com/rems-project/sail-riscv/blob/ae6cb1de092e9ea727e2318d76e9b88999bbee59/c_emulator/riscv_platform_impl.c#L15
E.g., for m mode, the physical address is not start from 0x80000000, or…
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hello
tried to simulate vexriscv
followed the instructions from Linux.scala
the linux files are
VexRiscvRegressionData/sim/linux
laur@laurPC-100:~/lucru/cn/riscv/vexriscv-linux/VexRiscv/src…
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Many IDEs allow for clickable links if you format error messages similar to common GCC/Clang C compiler output:
For example, in PyCharm, if I get an error/warning when compiling the simulator code,…
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Hi, I am currently trying to run simple RISC-V program with Sail emulator. I compiled it with cross compiler and trying to run it on an OCaml emulator. And I get the following error:
`CSR mstatus …