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# Target
- Become familiar with HW RTL design with CPU design orientation by designing a simple CPU in SystemVerilog.
# Background
- The MAFIA Project is a HW/SW co-design platform for the deve…
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Is SystemVerilog support planned in Digital?
Thanks
j054n updated
11 months ago
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I'm wondering if there is any ability to call a SystemVerilog/UVM Task/Function from Cocotb.
Instead of living in purely Cocotb, or purely UVM, is it possible from the python side to direct and con…
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Hope to provide verilog and systemverilog language plug-ins, support verilog and systemverilog syntax highlighting
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Hi. I'm trying on Ubuntu 20.04, but I also tried `ubuntu:latest` (docker image).
I installed Yosys from sources:
```
sudo apt install build-essential ca-certificates clang bison flex libreadline-…
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**The feature is not related to a problem**
**Describe the solution you'd like**
It would be nice to include slang (https://github.com/MikePopoloski/slang) as an additional linter to teros HDL. Cu…
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**Type of issue**: Feature Request
For a `FixedIOModule`, the `ioGenerator` is its header.
Think about this scenario, Different teams can only access the header for different purpose, e.g. RTL d…
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I'm on a Mac with the Apple M2 chip. Running the install script does install the plugin, but it's not compatible with the system.
Install:
```
curl https://api.github.com/repos/chipsalliance/sy…
zaun updated
2 months ago
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**Describe the bug**
Schematic viewer failed with the following systemverilog file:
**Code**
```systemverilog
`ifndef INCLUDED_types_def
`define INCLUDED_types_def
typedef struct packed {
…
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Hi
I am wondering if there is a plan to support compilation of the model to SystemVerilog using the -sv flag from sail.
I have attempted extending the makefile with this command:
`sail -sv $(SAI…