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The problem was introduced with the https://github.com/gatecat/nextpnr-xilinx/commit/565588a69ea95a52f7c7592f4ed81d9bef6cfb60 commit.
Basically, such a directory doesn't exist: `external/prjxray-db/a…
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Hi,
I am trying to use OpenCL SDK 17.1 (Quartus Standard ) with De1SoC
I am having a couple of problems
OS Ubuntu
Intel SDK installation
Quartus Prime Lite 17.1
Intel FPGA SDK for OpenCL 1…
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Hi! I know that if I want to show the "perf counters" in a RV32I architecture, I can easily use the "Perf Cfu" variant. However, now I want to use a FPU supported RISCV CPU, namely that I cannot use …
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This is what I get trying to create a virtual environment:
```console
$ uv venv
× Could not detect either glibc version nor musl libc version, at least one of which is required
```
Someon…
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Hello,
I've successfully synthetized the whole VHDL code to fit a spartan-6 and simulated it with Xilinx tools.
Now I would like to put my own sketch in the softcore program memory.
But to start wi…
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First, let's start with a diagram of how RocketChip is wired into LiteX:
Rocket has a ME…
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Regarding "FPGA SDRAM Communication: Avalon MM Host Master Component Part 3" wiki page.
It's better to reserve the memory with device tree instead of mem= kernel boot argument. If you reserve the mem…
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Hello,
first of all : Thank you for this great project! Good learning stuff, a very useful tool ... and fun :-)
### Goal :
My goal is to use **openFPGALoader** for programming a **QSPI-flas…
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In Pulpissimo platform, inside pulp-rt-examples uart testcases is struck.
Below is the output getting after using make all run command.
pulp-run --config-file=pulpissimo@config_file=chips/pulpissimo…
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Can I use these lowrisc-nexys4ddr bit files for genesys2 fpga board as it is? If yes then how can I use that or any modifications are needed?