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Hi,
Below is the script used to generate hex file for memory dimension [7:0] mem [depth] [bytes] but now our memory dimension changed to [63:0] mem [depth]
![image](https://github.com/chipsallian…
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This may be related to #1004 and #1105 but there signal was accessed in verilog module from VHDL top. My problem may also be missing feature due to use of 32 bit Modelsim delivered with Quartus softwa…
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I went ahead and took all the entries that had a `wikipedia.pageId` property and queried to see if they have a WikiData page.
Results
```
java Q251
javascript Q2005
c Q15777
python Q28865…
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### Describe the bug
Some gates (e.g. the `Mux`) will potentially output a `Z` if the input (e.g. the control) is a `Z` instead of outputting an `X`. We should fix the `Mux` and also search for any …
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Hi,
I wrote a mixed-signal SystemVerilog model of a ring oscillator. It uses timescale 1s/1fs. The period of the oscillator is about 1ns, but it takes about 20s wall clock time to simulate the whol…
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By default the HEX format generated with CMake is `verilog`, used in `tb_util.sv` to load the program directly into memory: https://github.com/esl-epfl/x-heep/blob/8f2351053dd240d4e6a01ac90cfcd49fb78a…
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This is not strictly related to CV32E40P as the problem seems to be in fpnew, but did anybody verify the operation of CV32E40P with fpnew in verilator?
There is a coding-style in fpnew, which preve…
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```
./verilate
rv64gc simulating...
%Error: ../testbench/testbench.sv:274:25: Can't find definition of 'EcallFaultM' in dotted variable: 'dut.core.priv.EcallFaultM'
274 | if (dut.core.p…
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Author Name: **Jeremy Bennett** (@jeremybennett)
Original Redmine Issue: 487 from https://www.veripool.org
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Verilog 2001 (and I believe 2005) allows considerable flexibility in short-circ…
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Can you attach an example that shows the issue? (Must be openly licensed, ideally in test_regress format.)
```Verilog
`timescale 1ns/1ps
task automatic run();
for (int i=0; i