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@Mluckydwyer I have run the demo on this https://github.com/Xilinx/systemctlm-cosim-demo/blob/master/docs/zynq-7000-getting-started-guide.md and was getting some value in shell using the devmem 0x400…
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Latest boot partition from master and latest released boot partition (2021_R1) do not define extlinux.conf on the file "files" definition.
This is necessary only for intel based carriers and it shoul…
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Old OmniVision sensors (including the OV7670) use the SCCB interface instead of I2C. It's basically the same, but the ACK bit is don't-care, and the SCL line is not open collector (always driven by th…
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@petut - any chance you or any of your contributors are Uni students?
If so, I would love to see a MigenAXI/Zynq intergration proposal as part of the [Google Summer of Code](https://summerofcode.wi…
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Per the [Xilinx Zynq 7000 TRM](https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf) on page 109:
, I am wondering if it is possible to point this monitor at yaAGC to debug and step thro…
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I received my board a few days ago and now I am in the process of testing it but after connecting it to my computer this is the only I get:
```
1.0.0.47 (Dec 07 2017 - 00:36:15 +0800)
Model: Zy…
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hi :
I've been studying zynq recently.When I finished the simulation under HLS
the last print :
88.38%: class 207 (output 18.94)
4.42%: class 852 (output 15.95)
4.25%: class…