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Hi,
While synthesizing SweRV-EL2 by using dc(2016.03), I got some error messages (unknown width).
Those are related to pt parameter, as follows,
```
1. $clog2(pt.xxx)
2. (pt.xxx)'(sig)
``…
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I have a multi-file (3 .cpp files and 2 .h files) C++ code that uses new, new[], delete, and delete[] operators to allocate large chunks of memory and performs some floating point operations (requires…
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Hi,
I am a software engineer at Rockchip. I want to evaluate this core. Is there a long-term support plan for this core？
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Hi,
Thanks for sharing this repository. I use Ubuntu 18.04, python 3.6m. After installing fusesoc, I try to run the simulation and an include file is not found although it exists:
INFO: Generati…
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When connecting OpenOCD I get the following warning:
Info : datacount=2 progbufsize=0
Warn : We won't be able to execute fence instructions on this target. Memory may not always appear consistent.…
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I just started working w/ fusesoc and swervolf and got this error when following the steps in the README.md file. I cloned the repositories today so should have the latest.
I am running ubuntu…
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hi, i was using eh1 to study memory access in cpu, and i have trouble understanding the pic module. Since pic module is suppose to handle interruptions, what does it have to do with load and store ins…
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Hi! I want to trace memory accesses and their target address during the program running on SweRV Core. Which signal should I trace? How about coming to the pipeline state(stall, bypass...)?
ymlei updated
4 years ago
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Hart.cpp is missing an
#include \
FpRegs.hpp is missing
#include \
which makes it fail to compile on my system
CentOS 7
gcc 10.2.0
boost 1.74.0 c++17