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I arrived at the following site which links to this repo and seems to be outdated:
https://symbiflow.readthedocs.io
compared to
https://f4pga.readthedocs.io
Can someone confirm this?
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I was trying this repo https://github.com/antmicro/yosys-uhdm-plugin-integration to add system verily plugin into yosys.
But when I try to run the build_binaries.sh script, it stuck at UHDM plugin pa…
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I have modified the OpenROAD flow scripts to use the systemverilog plugin to read SV files.
The line `parameter shortint unsigned W_LFSR = 16;` in my file `my_pkg_defs.sv` causes YOSYS to issue an e…
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I see this when I run `make all` in `systemverilog-plugin` :
```
In file included from uhdmastshared.h:4,
from UhdmAst.h:8,
from UhdmAst.cc:8:
uhdmastreport.h:…
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I view the code of function make_container_pb. The 'sinks' of routing mux is an array struct. But there are some 'assert' to judge if routing mux has multi ouputs. So in the case of mux with bus in a…
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https://github.com/SymbiFlow/symbiflow-examples/blob/master/xc7/linux_litex_demo/Makefile
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This will bring back functionality that was previously removed, as I was not aware of the `-i` flag.
tdene updated
2 years ago
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The user should know when their implementation does not meet their stated timing goal. It is not clear from vpr when this is the case.
#### Proposed Behaviour
Perhaps by default or perhaps onl…
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Some of the toolchain wrappers do not have a `usage` output, making it difficult to understand the required arguments to call the wrappers.
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[Prjxray-db](https://github.com/f4pga/prjxray-db) structure has been changed some time ago. As a result CI fails to build data files for most of architectures available in prjxraydb.
The errors (`F…