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Hi,
I analyzed the VHDL code from your UVVM project with Linty: https://oss.linty-services.com/dashboard?id=uvvm&codeScope=overall
Do not get scared by the number of issues :-)
It's just to pro…
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Hello for the third time! :smile:
The current letter case of code completion hints does not always match with the letter case of actually applied hints. In other words, the code completion hints do…
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Currently SystemVerilog modules are the only artifacts being produced with Utopia HLS. Additional output formats should be considered:
* ~Unscheduled DFCIR~ Closed with #25 and #31.
* ~Scheduled F…
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Ngspice team has recently added two XSPICE devices: `d_process` and `d_cosim`. These devices allows to simulate the component defined as Verilog/VHDL code with analog schematic. It's need to add suppo…
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Hello!
As the title states, is there a way to configure the VHDL Generator to generate VHDL with entity instantiations (e.g. `ff_inst : entity ex_lib.ff(rtl)`), instead of component instantiations …
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When attempting to build a design with the `IEEE.FIXED_PKG` package in vivado, the following errors are thrown:
```
chk-syn | CRITICAL WARNING: [HDL 9-3134] 'fixed_pkg' is not compiled in library 'i…
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The converted LPN has an initial value of 0, regardless of what values are
assigned to its corresponding VHDL file.
The example file, producer.vhd, located at
/home/ming/zhangz/nobackup/research/myTh…
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I'm very interested in ghdl_ls there are however some starting hurdles that I've got to overcome.
**1. How does a project have to be setup for multiple libraries (not only work). Multiple sections?…
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The VHDL Vivado example fails to generate the Vivado project with Vivado 2022.1:
```
PS C:\git\vunit\examples\vhdl\vivado> python generate_vivado_project.py
vivado -nojournal -nolog -notrace -mode …
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Hi! I'm far from an expert in reading vhdl, but reading this:
https://github.com/MEGA65/mega65-core/blob/c533da5ee6e26d33a6dd5018aac888fd3ece1fcc/src/vhdl/cia6526.vhdl#L549-L554
it looks like th…