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#### Expected Behaviour
VTR should compile warning clean with gcc and Inter-Procedural/Link-Time Optimization (IPO/LTO).
#### Current Behaviour
VPR compiles warning clean when `VTR_IPO_…
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General idea: looping through different net lists, and connect pins on the same connector pins.
So far, we should assume that on different net lists, if the components have the same `compRef` and `…
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### Environment (OS, Python version, PySpice version, simulator)
I am using Windows 10
Python 3.6.5 :: Anaconda Inc.
PySpice 1.2.0 installed from `pip install git+https://github.com/FabriceSalvaire…
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Nice library - thanks for sharing it!
I have installed it on Lubuntu 18.10 x64. The parser seems generally to work, however it does not handle any VHDL architecture content. For example, the file '…
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I've found out that below wire definition with delimiter generated below problem.
Could you fix this issue?
For example, below two wire definition generated below logs.
wire \fifo_in/enq_…
mgwoo updated
5 years ago
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---
Author Name: **Todd Strader** (@toddstrader)
Original Redmine Issue: 1305 from https://www.veripool.org
Original Assignee: Todd Strader (@toddstrader)
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Please see the t_func_const2_bad tes…
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I found netlist with following statement:
`.MODEL MOSPA PMOS(VTO=-2.0 KP=78.5E-4)`
What should be a default level of Mosfet in the parser?
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So far we prefer `pCad` netlist, since it looks like a `lisp` program, which is very easy to parse. Tom was suggesting some alternative format, the name which I forget.
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Hello,
I am working on very similar project https://github.com/Nic30/hdlConvertor .
I am using parser/lexer generated from grammar written in ANTLR4 and representing HDL by json like objects.
And…
Nic30 updated
5 years ago
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[filiperosset@raw ~]$ cd ~/rpmbuild/my/iverilog
[filiperosset@raw iverilog]$ git diff
diff --git a/iverilog.spec b/iverilog.spec
index 622fc5d..5ec860a 100644
--- a/iverilog.spec
+++ b/iverilog.s…