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Hello,
Right now when a `TestFailure` or `assert` is triggered, it stops the current test and writes a rather ugly Traceback message (like an uncaught exception).
```
280.00ns INFO cocot…
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Icarus Verilog cannot be used for simulation with fx68k, even when using the -g2005-sv option. As Icarus Verilog is the main FOSS tool for verilog simulation, it would be good to be able to use it.
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When using system tasks like $display, bsc insert a couple of #0 delays. I'm not sure if they are useful for event based simulator, but when using verilator it generates errors because delays are not …
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First of all, I would like to thank all who contributed to Verilator...🙏
I am a verification engineer who comes up with just ideas, I am not the right person to decide if it is possible or viable.
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Hi
I tried to simulate few axi benchs using xilinx vivado simulator.
I could parse all the code with xvlog succesfuly
But during elaboration I get errors like:
```
$ xelab tb_axi_dw_downsizer
…
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I want to generate a 4G Byte sparese Memory for simulation in VCS. The code is as below,
```
val memory = Mem(Bits(32 bits), 1 GiB)
memory.addAttribute(new AttributeFlag("sparse", COMMENT_ATTRIBUTE…
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Verilator version: master fadc677
Currently, for **simulation time callbacks** (see IEEE 1800-2017 38.36.2) other than `cbAfterDelay`, Verilator ignores the _cb_data_p->time_ field, and they are re…
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Hello,
Brand new to UVVM. Not sure if I understand the idea behind Message IDs.
1. ID_FINISH_OR_STOP. What does this ID do? If I use it in log(ID_FINISH_OR_STOP,...); does it actually Stop or …
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I'm using `warnNonSynthesizable` expecting it to error only when actually using (synthesizing) the code labelled as non-synthesizable, e.g. if it's possible/easy to statically determine that the code …
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I have encountered an issue with RgGen generated code in our random regressions writing to 2 adjacent registers and subsequently reading back those values. Some timings work correctly and some fail r…