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In Python one can just write ``x.right``, but in VHDL ``x'right`` is correct.
Needs to be solved via RedBaron convertor..
Current workaround is to use ``left_index()`` and ``right_index()`` functi…
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**Bug Description**
The header license entered at the top of the template of VHDL files uses Verilog comments style (`//`) instead of VHDL comments style (`--`).
**To Reproduce**
1. Configure a l…
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**Is your feature request related to a problem? Please describe.**
I'd like a rule to enforce case on the `others` keyword in selected assignments. For example, I'd like
```vhdl
architecture rtl of…
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I have a design with a RAM with line enables and a single line. When simulating it in Logisim reading from the RAM is asynchronous, but when running it on an fpga reading seems delayed by a clock cycl…
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Readme mentions Vim as one of the options, but it's not straightforward to me how to do that. Is there a working example on how to set this up with "vanilla" vim + e.g. Ale or any of those frameworks?…
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These are the VHDL kinds parsed in the latest implementation of ctags:
```c
static kindDefinition VhdlKinds[] = {
{true, 'c', "constant", "constant declarations"},
{true, 't', "type", "type de…
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https://github.com/themperek/cocotb-test/blob/32b19b0813ae40cefc2b6d5bf1a1a715682fb18c/cocotb_test/simulator.py#L718
Hello! Please, explain me, why vhpi option for vhdl_source is added to xcelium in …
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More often than not, when I'm trying to import a complex HDL code into the simulation, and I get a popup with a bunch of errors for a file which is only the extension (`.v` or `.vhdl` is the filename …
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We'd like to allow both SystemVerilog and VHDL test benches in our project. From #297 I learned that
```python
from vunit import VUnit
```
should be used for VHDL, and
```python
from vunit.veri…
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It gives the following result:
```
Error: outputVerifier, expected: 000000010000000100000001, actual: 000000010000000000000000
Time: 40 ns Iteration: 1 Process: …