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I am trying to use LitePCie for my project with the [Trenz TE0712](https://wiki.trenz-electronic.de/display/PD/TE0712+TRM) board. The target and platform files are not there in the [litex_boards](http…
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Do you plan to support other FPGA boards in addition to the current Genesys 2?
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I want to learn FPGA development and these tutorials are amazing - thank you so much!
However, there are zero available IceSticks in the market right now. A cheap and accessible FPGA is the Upduino…
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Hi.
I just started with migen/LiteX and FPGA.
I want to add an UART to colorlite.py
So I copied and modified the parts from ios_stream.py. Sending four bytes over UART works fine. But it keep on …
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Hi, I'm a student interested in FPGA and want to learn more about SDR, especially AD936X based ones. I wonder if it's possible to have AD936X extension boards for low-cost FPGA platforms like the PYNQ…
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Hi all,
I have build and compiled the newest available version of OPAE-SDK on a CPU which runs ubuntu 21.10.I am encountering an error while running fpgainfo fme,and also I request to kindly suggest …
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I am trying to add new commands in the demo main code and then run it it gives me:
> /home/fathymd/litex2/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-centos6/bin/../lib/gcc/riscv64-unknown…
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Dear charles,
How you recommend me to compile the updated code with
```
sbt "runMain naxriscv.Gen64"
```
like which branch to stay in spinal HDL and which branch to stay in main one ?
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I'd like to experiment using Microwatt as a 64-bit microcontroller on an ECP5 LFE5U-25F. Unfortunately, even with the following patch, I can't seem to get Microwatt _and_ SoC peripherals to fit:
``…
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On my machine, the command `./kosagi_fomu.py --cpu-type None --build` gives
```
INFO:iCE40PLL:Creating iCE40PLL, SB_PLL40_CORE primitive.
INFO:iCE40PLL:Registering Single Ended ClkIn of 48.00MHz.
…