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I've been thinking long about having some multiplatform (windows and gnu/linux), free (libre), lightweight and standalone tool to analize large bodies of VHDL 2008 code at block/RTL level. That tool w…
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VTR won't compile on cygwin due to use of strdup and strnlen in two ODIN-II files: netlist_visualizer.cpp and soft_logic_parser_def.cpp.
Neither strdup nor strnlen is standard C, so we should not u…
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Hi Tsung-Wei
I noticed another issue while running with tcl based Opentimer
To reproduce the issue, use the below steps:
Download [testcase.tar.gz](https://github.com/OpenTimer/OpenTimer/files/24…
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## Steps to reproduce the issue
I am running read_verilog on a netlist file (automatically generated by a commercial tool).
A minimalist code to reproduce is:
```verilog
module foo();
wi…
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This function has a behaviour that is mysterious to most -- it should be better commented. It is for architectures where you have logically equivalent outputs, but they are achieved not by having an…
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---
Author Name: **Filipe Rosset**
Original Redmine Issue: 1299 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
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Fedora bug report: https://bugzilla.redhat.com/show_b…
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Yosys can output an ["extended" blif format](http://www.clifford.at/yosys/cmd_write_blif.html) which includes a lot of useful extensions which enable BLIF usage for real world FPGA support (related to…
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when I generate a netlist from linux (the test in your repo has a windows path) I get no arguments to the date, title, rev, and company arguments
(sheet (number 1) (name /) (tstamps /)
(ti…
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Hi,
I am getting unable to get org url. Check username and password .. meassge.
The app is executing fine and the spark bot is able to send messages. Exception thrown is Response code [404] The URI…
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TODO:
- [x] in `qucs-core/scr/circuit.h` remove unneeded virtual functions. The `dc/trsolver` can set the state for ohmmeter and the special cases can be handled inside the `ohmmeter::initDC`
- [x…