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Hello,
I am just trying to run swerv design on xilinx zed board using vivado and instead of running it in the debug mode using jtag and uart i want to interface this with zedboard io's.
Could you…
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To get the full performance of SweRV, I am aware that you should use the tightly coupled memories (ICCM and DCCM).
When using larger external memory, the common way is to attach them via AXI. Then y…
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Hi,
I was using SweRV_fpga (https://github.com/chipsalliance/Cores-SweRV_fpga) with version 1.4 of SweRV with no problems. Everything was working fine.
When I've changed the core to SweRV 1.5, Ope…
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Author Name: **Wilson Snyder** (@wsnyder)
Original Redmine Issue: 1566 from https://www.veripool.org
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From https://www.veripool.org/boards/2/topics/2831-Verilator-FST-dumping-100x-slower-…
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@aprnath ,
I see that the maximum size of DCCM is limited to 512kB. I am trying to use the SweRV for an application that needs a larger DCCM , 4 - 8 MB. How easy is it to achieve this?
Thanks!…
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SWERV CPU doesn't work properly if memory interface HREADY signal (highlighted on the waveform) is high by default:
![image](https://user-images.githubusercontent.com/55279763/75802436-59fce180-5d85-…
vit82 updated
4 years ago
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I am trying to make interrupts work in the SweRVolf SoC. The concrete objective is to make switches work by using vectorized interrupts. I am following the Swerv documentation, trying to replicate the…
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The always@ reduction fails in swerv design with the following error
```
INFO: Performing wire/reg declartion optimizations.
INFO: Performing always@ reduction optimizations.
Traceback (most rec…
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Hi,
I am trying to use the interrupt on the SweRV core. I am trying the following
1) Setup interrupt[1] with following features -
standard priority order - 0x0 @ mpiccfg
gateway configu…
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Hi,
I executed breakpoint test on sweRV core (https://github.com/chipsalliance/Cores-SweRV) and it failed. After some digging and asking the community (https://github.com/chipsalliance/Cores-SweRV/is…