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Hi, I'm a student interested in FPGA and want to learn more about SDR, especially AD936X based ones. I wonder if it's possible to have AD936X extension boards for low-cost FPGA platforms like the PYNQ…
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Per discussion on Discord, it appears as if a sufficiently long table, wrapped in a `#figure` in order to apply captioning, and with the block set to breakable, does not correctly discover the table h…
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Hi and thanks for attempting to make something useful out of those old Infrant based NAS.
As those SoCs are based on the LEON (v2, v3 ?) 32bit SPARC architecture, i wondered if anyone ever played w…
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Dear charles,
How you recommend me to compile the updated code with
```
sbt "runMain naxriscv.Gen64"
```
like which branch to stay in spinal HDL and which branch to stay in main one ?
…
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I don't seen any import in code.
Is this dependency really needed on all platform? Installation on windows seems difficult...
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According to the documentation, some regular VexRiscv-smp configurations are already pre-generated, but when running `sim.py`, it starts by creating an SoC instead of booting:
```
INFO:SoC:Initial…
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Sometimes when starting Jackd channel 1 becomes channel 7, sound moves form the fisrt rca jack to the seventh one. This occurs roughly 1 time out of 10. Restarting Jackd returns channel 1 to rca 1.
I…
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We are trying to use our 6T SRAM design instead of the BRAM for simulation. I understand that we would still need the BRAM to copy the image(vmem or elf) into the memory. My idea is to copy the …
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Made following steps:
>git clone https://github.com/altera-opensource/linux-socfpga.git
>cd linux-socfpga/
>git branch
socfpga-6.6.22-lts
>make ARCH=arm socfpga_defconfig
>make ARCH=arm me…