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Hi,
I'm using fusesoc+edalize for synthesis on zynq mpsoc platform.
Now I would like to also simulate some of my subdesigns with xsim (or any other simulator for that matter), which is not a stra…
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I have some IP-XACT from some IP that is using expressions of the form:
('ffffffff) / $pow(2,0) % $pow(2,32)
This is a quite strange yet effective way of doing this but it comes from converting …
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@SiFive and @drom have created a thing called [DUH](https://github.com/sifive/duh). This format describes things like wishbone busses and stuff.
This seems like a good thing to integrate with FuseS…
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Hello
I try to use xsdata library with following schema : [http://www.accellera.org/XMLSchema/IPXACT/1685-2022/index.xsd](http://www.accellera.org/XMLSchema/IPXACT/1685-2022/index.xsd)
I genera…
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I'm trying to use Kactus with a bunch of scripts/tools that we've used for a while. I encountered a problem while doing that with the XML namespace handling in Kacuts. Our tools use an XML libraries t…
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Many HDLs are written in Python (see http://bit.ly/pyfgpalibs for example). It would be awesome to have a good Python library for working with DUH.
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## description
In hardware designer, design parameter menu is set as visible by default when opening a diagram. Despite this it does not appear on screen (by default on the bottom edge below design…
Kyrhe updated
3 weeks ago
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Hello Developers,
First of all my sincere thanks for putting together this extension for vscode. Over the past few days I played around teroshdl-vscode. I would say that its a great step in bringing …
cng18 updated
2 years ago
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Currently, we have a couple of purely structural Verilog files in OpTiMSoC: the toplevel files at various levels of the hierarchy. Creating these files is tedious and error-prone (getting wiring wrong…
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I am facing a problem which is much larger than I anticipated it being: module parameterization or -- more generally -- configuration of the subsystems we produce. The SystemVerilog we have is intende…