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I'm interested in using Hdl21 for creating a test bench for a design already defined in a traditional schematic. In this case, it is coming from an [xschem](https://github.com/StefanSchippers/xschem)…
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Yosys supports several non-standard features of the BLIF specification that bring it more up to speed with a modern netlist format. Some other FPGA consumers of the BLIF format use this already.
Fo…
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#### Expected Behaviour
If the proper syntax is in place, it is possible to override the parameters in a seperate model with new values. There are two ways to do it, defparam and model #(.param…
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Hi, I made this for parsing plain text schematic values:
https://gist.github.com/endolith/1a74477fc1659cd6bf9d138e09c72672
```
value_parser('100 MΩ')
Out[194]: (100000000.0, u'ohm')
value_parser('2…
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While working on https://github.com/symbench/electric-circuits/issues/23, I found that the following netlist (Taken from the dataset [repository](https://github.com/symbench/spice-datasets/blob/master…
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Unable to generate a TMR netlist
ValueError: Applying name would result in a naming conflict
namespace_manager -> init.py
Line 107 - if parent and parent in self.namespaces:
possible fix - if …
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I'm getting confised by the usage of your parser. After populating yy_verilog_source_tree using the provided functions described on https://codedocs.xyz/ben-marshall/verilog-parser/group__parser-api.h…
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Currently the xml parser in vpr is hand coded.
It would be good to rip it out and replace it with a auto-generated xml parser based around a DTD which defines the file format.
Create a XML defi…
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#### Expected Behaviour
An always block executes when the signal inside changes. For instance, if the always block is written as: always@(a or b), the statements in said block will execute when…
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Represent Xilinx built in primitives and provide functions for more easily dealing with Xilinx-specific primitives.
- Give the library ahead of time to the parser so that the parser checks against…