-
I am conducting tests on the RISCV multi-core processor AIA to enhance the efficiency of automatic testing. Independent of Linux, I am using OpenSBI as the fundamental environment to run test codes. C…
-
The latest release of the privilged spec:
* https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-3f725b5-2024-05-31
has this (_emhpasis_ is mine):
> **3.1.5. Hart ID (mhar…
-
Hello,
I am encountering an issue when I used nx_packet_allocate because ULONG is considered to be 8 bytes for the RISCV-64 bits architecture.
It worked perfectly on my previous target CORTEX-R4…
-
I have used FSM ULP on ESP32 to read the processor temperature, using tsens instruction assembly, but now I want to read the processor temperature through riscv ulp on esp32s3, but I can't find releva…
-
Hey,
I am working on trying to integrate the riscv-formal interface to the noelv processor. I have started running the formal verification tests and encountered an error mentioning `PREUNSAT`, `Assum…
-
## Background
I am currently involved in a project aiming to support the CTR extension on some RISC-V processor RTL. Given the significance of software in testing and debugging process for CTR, I am …
-
As mentioned in #33 (a conversation that went way off-topic), the code uses a mix of spaces and tabs for indentation.
I prefer spaces, so I've been using spaces in all new code, and converting old …
-
From: sims/verilator
make SUB_PROJECT=cep_verilator
...
/mnt/data/projects/ipvault/jkrim/cep_v4_4_new3a_test_verilator/CEP/.conda-env/bin/x86_64-conda-linux-gnu-c++ -Os -I. -MMD -I/mnt/data/pro…
-
When running a randomized load store test with `riscv_load_store_rand_addr_instr_stream`, the ISS will throw an exception, saying that we are trying to access an invalid memory region.
```
27 Info …
-
Respected sir
Subject: Request for Assistance - CVA-5 Processor Simulation
I trust this email finds you well. My name is Tanishq.S, and I am a student from PES University, India. I am reaching out…