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Hi Alex,
Thanks for sharing your verilog-pcie library! I have been running simulations for the various components and examples as well as studying the source but still have a few questions. For all…
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**Type of issue**: other enhancement
**Impact**: no functional change
**Development Phase**: request
**Other information**
It would be nice to have a knob that adds test muxes for all …
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### Description
It seems useful to provide a Spice model that includes extracted parasitics at the end of the flow. Proprietary tools readily make this available, and it makes sense to provide the …
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The BP for horizontal blanking is 8 pixels when looking at the output of the board.
![image](https://github.com/user-attachments/assets/dbb42217-cf7d-4533-be31-0b4b5431ddcc)
These are based on veril…
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I was studying how calculate these values to give a approach about gate level simulation using yosys to generate a verilog under cell libs on vsclib013.lib . But you need STA time calculation Path to …
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I used the gen.py file to generate a litedram core, and meanwhile a build_xxxx.sh was generated as well.
When I tried to run build_xxx.sh file , it point to a make file in "litex" folder which call a…
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Hi,
I am building a microcontroller based on Ariane and I am reusing a lot of the peripheral I was able to find here.
I implemented the system on FPGA (zcu102 board) and I connected the RISCV-base…
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### Checklist
- [x] Did you write out a description of the feature you want to see?
- [x] Did you look around for any related features?
- [x] Did you specify relevant external information?
###…
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I try to appy the code in latest version,it can't complie them.
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The Verilog-A model does a manual integration of the filament thickness here:
https://github.com/google/skywater-pdk-libs-sky130_fd_pr_reram/blob/6574676cbbd062d63be0f090013d59ced7302349/cells/rera…