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It would be awesome to add Western Digital SWERV RISC-V core as a test bench. You can find it at https://github.com/westerndigitalcorporation/swerv_eh1 and it is released under an Apache 2.0 license.
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**Severity:** High
**Version:** commit e9815864ca5757e59927e9dd8af36694d9918871
**Details:**
The following designs are not able to complete due to issues in TritonCTS
- nangate45/swerv
- tsmc…
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Just a heads-up. I'm working on head-to-head Verilator CI with external projects and found that the latest Verilator tosses some width warnings on the SweRV build:
https://www.veripool.org/issues/14…
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Due to introduction of template method in Core/HartConfig class in this commit: https://github.com/westerndigitalcorporation/swerv-ISS/commit/882de25a8be2f7944f22205671c6d4a2239bc75d#diff-fdf14d2fb8fe…
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DCCM data outputs are forced to 0 values at he [testbench](https://github.com/chipsalliance/Cores-SweRV/blob/1651bdf99a9c7dafab543e8697c48bf300e56cfa/testbench/tb_top.sv#L364).
Does this mean DCCM is…
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Hi,
I see some problems with $fwrite formats and $time:
my verilog code looks like:
```
$fwrite (el, "%10t : %6s 0 %h %h %s\n",$time(), $sformatf("#%0d",commit_count),
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The Verilator external test suite is breaking on the SweRV test, and this time I don't believe it is a Verilator regression:
https://travis-ci.com/verilator/verilator_ext_tests/jobs/228899219
It a…
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**Priority:** High
I have observed several bad placement of macros in the OpenROAD flow.
**overlapping macro placement**
bp_fe_top_tsmc65lp
![image](https://user-images.githubusercontent.com/1…
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Instead of using the case statement for select encoding and having an a mux cell, may I know what is the reason for the unconventional way of doing the mux logic in this repository?
It is quite no…