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Setting up the Xiling Spartan-6 involves installing a VM which is capable of running ISE 14.7.
From here we can write the firmware in VHDL if we connect the JTAG to the FPGA.
The development ar…
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While we don't know about good open-source linters for VHDL and SpinalHDL, **(System)Verilog** has got at least three: **Verilator**, **Verible**, **Slang**. Check [this](https://github.com/chili-chip…
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https://sonar.linty-services.com/coding_rules?open=vhdl%3AVHDL138&rule_key=vhdl%3AVHDL138
il faudrait je pense faire deux règles une pour les entrées et une pour les sorties.
sachant que pour les en…
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I would like to be able to use this extension without specifying a vhdl_ls.toml file.
In fact, the extension works very well without it being able to load the aforementioned file already.
However,…
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- [x] Create Detailed Block Diagram
- [x] Write VHDL
- [x] [Implement ACR, AVR, HC](https://app.gitkraken.com/glo/card/09a1c1a33a7c441e9ba3d9a3663af043)
- [x] Test VHDL
- [x] Report
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Below are the description of pulsing finding for the IWCD mPMTs. We will need to implement it in the waveform fitting function to get digitized Q and T.
---
The general description of the hit fi…
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Hello,
I have a very basic test bench with a vhdl top and two sub-modules: one vhdl and one verilog.
When trying to access the verilog submodule from a cocotb TB I have an error:
Unable to cr…
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Hello,
To achieve a better readability of my VHDL code, I wrapped the AXI4Lite bus signals in a axi4lite_bus_type VHDL record.
```
type axi4lite_bus_type is record
-- AXI input bus inte…
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When running projects with pre-compiled/vendor libraries or mixed language projects, not all files will be in vhdl libraries added to the vhdl_ls.toml file.
It would be very useful to be able to add …
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## Describing the bug
By pressing the 'Schematic Viewer' button on the 'Dependency Tree' panel, the Schematic Viewer window shows a blank page.
In the same time, the Output page for 'TerosHDL: Glo…