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TL;DR: Multi-Core System does not boot Linux. Framebuffer makes everything worse
Hello! I have the goal to build a quad-core RISC-V system that I load
onto an ULX3S Board (ECP-85F). In the long te…
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Right now, large CSRs spread across multiple "simple CSRs" whose size is ***NOT*** a multiple of 4 bytes are distributed in a counter-intuitive way. For example, a 17 byte CSR whose hardware value is:…
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I am trying to add the top level in a quartus project but many hdl files are missing from the core dir that the top level calls out.
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I'm using (64-bit) RocketChip as part of the LiteX SoC environment, which provides DRAM controllers of varying AXI port width, depending on the specifics of individual FPGA boards it's being built for…
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Hi,
I tried to load and run Bootrom, BBL and Linux Kernel on FPGA.
Bootrom and BBL can print on UART console without any issue, but the Linux Kernel cannot, even it went pass through a few place…
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Quartus Pro 20.1 claims pin clashes:
```
Info(175029): IO12LANE_X61_Y327_N2
Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IO_LANE(s))…
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Hi,
I would like to run a GUI with this SOC on FPGA. so I can check a breakpoint etc.
there is a prepared GUI that I can do with it things like this?
thanks
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When the SoC is configured with a crossover UART, it could be useful to create a /dev/ttyX device on the Host to access the UART of the SoC directly.
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I successfully booted Linux with FPU disabled. When I enable FPU, I get the following errors:
```
[ 0.156632] smp: Bringing up secondary CPUs ... …
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As discussed on ##linux-surface, hardware buttons on some Surfaces are not working. Reloading the button module works post-boot:
```
sudo modprobe -r soc_button_array
sudo modprobe soc_button_array…