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I noticed ODT is pulled low and not used. Why is it so and would not having it cause failures when operating in rare conditions ?
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The w11a design for Arty S7 (50 die size), see [rtl/sys_gen/w11a/artys7](https://github.com/wfjm/w11/tree/master/rtl/sys_gen/w11a/artys7), was provided to support also an up-to-date Spartan-7 based bo…
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On the Arty board we don't have a second channel of the FT2232 chip available for JTAG to the CPU core. Options are either using a separate JTAG PMOD, or tunneling JTAG through the Xilinx BSCANE2 prim…
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Hello, does anyone have problems compiling the firmware from the lab004?
I'm using KDE Neon based on Ubuntu 18 and the last Litex and RiscV toolchain version, my target is an arty_s7.
When I try t…
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Hi, I am using Vivado 2020.2 and testing the HyperRAM controller with an ARTY-S7 board and a PMOD board with HyperRAM. I am able to pass the memory test up to 108MHz. When I go to 128 MHz the memory…
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Hello, does anyone have problems compiling the firmware from the lab004?
I'm using KDE Neon based on Ubuntu 18 and the last Litex and RiscV toolchain version, my target is an arty_s7.
When I try t…
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Okay, so the Verilog is in rough shape for a few reasons. The biggest is that it was clearly written as Jon was learning (
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Super-Ottan と申します。
「作ろう！CPU」楽しく拝読しておりましたが、
Windows10 環境での Vivadoの環境構築がうまくいきません。
結果、プロジェクトの作成が完了しません。
Vitisのバージョンアップにより、かなり肥大化しています。
インストールの際、Vivadoのみのインストールを選択した場合、サポートページの
「Vivado HL WebPACK」はあ…
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Hi hope everyone is alright. :)
I've been trying to use the debug plugin with the JTAG, when I launch my program without breakpoints the program executes without no problem but when I put a breakpo…
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If i want to add a new instruction EX: "ADDOR"
A+B = C
C = A | C
return C
/root/riscv_cpu/VexRiscv/src/main/scala/vexriscv/Riscv.scala
/root/riscv_cpu/VexRiscv/src/main/scala/vexriscv/plugin…