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(The title of this issue refers to my best guess at explaining the behavior below, as I have not dived into how the GHDL synthesis code actually works. Please let me know if some other title would be …
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I just thought it'd be good to have a place to keep track of how far removed we are from being able to upstream this project into Yosys, assuming they want it.
At this point GHDL is able to synth f…
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**Description**
Attempting to load the example below in yosys with the GHDL plugin results in the assertion failure shown below. Simulation of the larger design which the example is derived from work…
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## Steps to reproduce the issue
When specifically trying to synthesize a [Microwatt CPU](https://github.com/antonblanchard/microwatt) SoC using `yosys`, I've noticed that the `autoname` pass takes …
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I have this **VHDL** design in a file `spi_icebreaker.vhdl`:
-- A:
library ieee;
use ieee.std_logic_1164.all;
-- B:
entity spi_icebreaker is
port(
pcb_osc…
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This would greatly help with simulating mixed-language projects, which could look like the following:
Verilog testbench (which should be possible now):
1. Use yosys to synthesize the modules (whic…
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It would be nice if the output of the synthesis could be written to a file instead of to stdout.
This cannot simply be achieved by redirecting the output of `ghdl --synth --out`, because the output…
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Used msys2 32bit in Windows 7 to integrate everything together.
I've compiled ghdl 81905a8c.
Then used ghdl-yosys-plugin 0b687cd.
In-compiled it directly into the yosys 334ec5fa.
[fails.zip](https…
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It looks like Yosys frontend for Verilog is not fully compatible with the Verilog output of GHDL synth when it comes to module parameters.
It chokes on the following:
> module ODDRX1F
> #(
>…
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Create good support for VHDL.