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This is a placeholder for tracking world build failures on rv32, the current list and respective error logs are [here](http://errors.yoctoproject.org/Errors/Build/102097/?limit=50)
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in arch/riscv32/paging.rs
// Set kernel identity map
p2[0x40].set(Frame::of_addr(PhysAddr::new(0x10000000)), ......);
p2[KERNEL_PML4].set(Frame::of_addr(PhysAddr::new((KERNEL_PML4 as u3…
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For implementation of fmvh_x_d,
when write back, the result should be sign-extended
> WRITE_RD(ui.ui >> 32);
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As discussed in this week's CHERI TG meeting, it is sometimes desirable to use alternative capability encodings, particularly in RV32. However, the CHERI RISC-V specification currently mandates capabi…
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### Technical Group
Code Size Reduction TG
### ratification-pkg
Code Size
### Technical Liaison
Tariq Kurd
### Task Category
Arch Tests
### Task Sub Category
- [ ] gcc
- [ ] binutils
- [ ] gd…
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64bit apps are very likely to have a different needs.
RV32 only ext can recycle OP-32 and OP-IMM-32
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1. Like RORI has RORI_RV32 version, I think SLOI and SROI also need *_RV32 version.
https://github.com/chipsalliance/rocket-chip/blob/f1521796c292ee87958df6ea52f12145d869c83f/src/main/scala/rocket/In…
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After a successful build and flash, RV32IMA attempts to start but the task watchdog triggers and aborts main. I think it's getting stuck in an infinite loop?
Below is a snapshot of the terminal mon…
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Hi,
CHERIoT is spec'ed as being 16 GP registers only. However, in Sonata the RV32E is set to 0 which means that there are 32 GP registers. Shouldn't the RV32E parameter be set when the CHERIoTEn pa…
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Currently to choose between F support or F&D you need to compile the model differently - using `riscv_flen_D.sail` or `riscv_flen_F.sail`.
This is unfortunate because now to support all the differe…