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Capture all the objects, classes, groups pertinent to the SystemVerilog Constraints in the yaml format.
Create UHDM unit tests (C++) showing proper representation of common constraints constructs (…
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To be useful to me I need to be able to output to SystemVerilog instead of Verilog. I've added support for SV here: https://github.com/dj-on-github/myhdl which is working with basic examples but needs…
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This guide lists SV interfaces as [problematic](https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md#problematic-language-features-and-constructs) and that their use is discourage…
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A couple of questions first
- Your IDE/editor (e.g. vscode, emacs,...) you use with verible LSP: VS Code
- IDE version: Latest
- What other SystemVerilog plugins are active alongside: None
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Verilog is already supported, and it would be great if SystemVerilog had support too. It uses the same commenting format.
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My appologies if i've missed this in the docs, but I'm unable to use as a front end for formal verification
This just fine: bmc, prove and cover statements all run ok
```console
read -sv -formal …
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SystemVerilog is almost identical syntax to Verilog. It could be quite easy to support SystemVerilog filetype (.sv) using same rules as Verilog which is already implemented.
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I noticed that the VUnit testcases in a SystemVerilog testbench will always fail if their testcase name contains a colon. I attached a minimal example including a simple run.py script and a minimal te…
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SV contains the notion of a `constant_expression` :
![image](https://github.com/veryl-lang/veryl/assets/21023236/7121bbba-0c5d-48af-83d3-f77caad395bf)
This is used in quite a few different part…
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Is there a way for ICSC not to write all SystemVerilog modules to one file?
I think sometimes it would be more convenient to split the modules into several files to make them easier to read.
Wh…