-
If you run `python scripts/run.py tests/ci/randsoc_dumped.yaml` twice in a row, it will fail with a cyclic dependency. This occurs because the synth_tool picks up all the verilog files in the directo…
-
From testing #1610. In verilator, Questa, Riviera, and Xcelium signals with extended identifiers are discovered with the `vpiName` starting with the backslash and ending with a space.
```python
du…
-
### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
Hello, I'm trying to run ariane_tb.sv on Cadence Xcelium 22.03 from `xrun_all` Ma…
-
-
Subscribe to this issue and stay notified about new [daily trending repos in Verilog](https://github.com/trending/verilog?since=daily)!
-
### Version
Yosys 0.39+165
### On which OS did this happen?
Linux
### Reproduction Steps
Consider the following code. When the input is `wire0 = 6'b111101`, it is a negative number less than `for…
-
Hi,
after seeing [`https://github.com/nickg/nvc/issues/808`](https://github.com/nickg/nvc/issues/808) I gave it a shot at compiling Verilog standard cell libraries I have available for a PDK that w…
-
Hello, I only edited my `layers.json` file and left the Python files unchanged. I used [five_transistor_ota_Bulk.sp](https://github.com/ALIGN-analoglayout/ALIGN-public/blob/master/examples/five_transi…
-
For the following code:
```python
import math
from hwt.synthesizer.param import Param
from hwt.synthesizer.unit import Unit
from hwt.hdl.types.bits import Bits
from hwt.interfaces.std import S…
-
Hi, I am looking for that controller in Verilog/system Verilog. Can you help me please?