-
```
Vamos a entrar a laburar con el xilinx.
Tenemos que generar una memoria como la que hicimos en clase y fijarse como es
el formato .coe para que la memoria levante las instrucciones.
```
Origin…
-
ISE is discontinued after 2013. Are there any plans to make your designs compatible with Vivado 2014?
Currently, one is not able to make the project due to the following errors:
```
CRITICAL WARNING…
-
Hi,
How to port your GMac implementation to 10, 100 MAC ? I am using LX9 microboard, and want to give your implementation, as well as chips-2.0 a try !!
Thanks!
Liu benyuan
-
I recently rebuilt the FPGA, and got the warnings below. From what I could tell, these warnings were not there before the izsh-changes. I don't know what to make of it, so I'll just put it here and se…
-
Hi,
I just started using fusesoc. I was trying to build a generic soc for the Atlys board using the command "fusesoc build atlys", and I am having an issue where the build errors out in the "Place &…
-
We need to add the Zynq (ARM + FPGA) platform as a target for the ACCEPT toolchain.
This involves:
- [x] Extend `app.mk` to cross-compile binaries for the bare-metal ARM.
- [x] Also extend it to exec…
-
Hello,
I attempted to build the atlys system using the newer xilinx tools and got an error. Apparently the method used to divide the clock in dvi_gen_top.v is now illegal.
From Xilinx:
In Spartan-6 …
-
IP core versions of IP cores from the Xilinx catalogue do not match the available/compatible core versions of the selected ise backend.
Thomas Fischer (8/7/2013 11:09 AM): This is a problem with the …
-
The VHDL generated from [TopVhdlPrinter.xtend](https://github.com/orcc/orcc/blob/73a6342526884e9a445f9bd1bee0ed682fef6734/eclipse/plugins/net.sf.orcc.backends/src/net/sf/orcc/backends/c/hls/TopVhdlPri…
-
Hi all,
I created the pcores by running [make] in the core directory, NetFPGA-10G-live-devel. and I changed directories to /NetFPGA-10G-live-devel/projects/loopback_test_nf1_cml and run [make]. Woul…