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Hi,
I'm trying to migrate the generated firmware for my keras model to Alveo U250 card using Vitis. I have attached my model definition below. I was able to do that with `Strategy: Resource` but no…
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Hello.
I have a question about the usage of nanotube-generated HLS modules.
I'd like to know what I should connect to the input and output of the AXI-Stream chain.
### What you are trying to do.
…
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Supporting DPDK would permit the use of userspace network stacks, enabling development of features across the entire stack. Implementation of a DPDK PMD should be investigated.
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Hi. When using `DesignTools.calculateUtilization(...)` on a design implemented on Alveo U250, the two columns of DSPs on the right side (beside the Vitis default static region) are locked and hence tr…
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### Description:
I am using the litex-hub/linux-on-litex-vexriscv repository with an Alveo U250 FPGA board. I have successfully built the bitstream and loaded it onto the FPGA board, but I am havin…
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**Describe the bug**
I am trying to build TriSYCL for Redhat 8, and I am running into an error where libpi_opencl requires libstdc++fs, but it doesn't seem to be linked into the standard CMake build.…
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@rwarmstr got another question if you have time: I profiled the `wide_vadd` tutorial with some small
modification to add float instead of integers. I also used 4 concurrent kernels.
Environment: …
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Thanks a lot for open-sourcing the verilog source code and corresponding bitstreams. I followed the instructions for the basys3 board trace collection and performed the CPA using the provided scripts.…
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Hi. I would like to get all sites of a pblock in Alveo U250. Here's an example where I find a discrepancy between RapidWright's result and Vivado's TCL script.
Let's say we have a pblock defined a…
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**For Vivado questions, please use [Vivado forum](
https://forums.xilinx.com/t5/Vivado-RTL-Development/ct-p/DESIGN)**
**For Vitis questions, please use [the Vitis forum](
https://forums.xilinx.co…