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https://github.com/sifive/duh-scala/blob/master/lib/axi4-tl.js#L162
`TLWidthWidget` expects an `Int` argument but it is passed `bap.pbus` which is of type `TLBusWrapper`
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In Chipyard/generators/Rocket-chip/src/main/scala/SubSystem/Config.scala
In Class WithDefaultMMIOPort, I change the ExtBus => ExtBusAHB
In Chipyard/generators/Rocket-chip/src/main/scala/SubS…
HC-Lo updated
2 years ago
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**when i build verilog, i got the error as follows:**
rocket-chip/src/main/scala/amba/axi4/Credited.scala:12:64: not found: type Parameters
[error] class AXI4CreditedBuffer(delay: AXI4Credi…
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I'm trying to write a TileLink DDR controller to replace the default AXI4 memory port. So what I need to write a TileLink DDR controller?
ghost updated
3 years ago
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Narrow bursts with axlen >= 1 are not supported yet. This is quite rare operation mode, though I have plans to support this feature too to keep IP core 100% AXI4 compliant.
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Hello,
I'm looking to generate the Verilog/Vhdl of a VexRISCV multicore SMP processor but rework its IO buto AXI. I see it has been done for a single VexRISCV core:
https://github.com/SpinalHDL…
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Using the AXI4 Memory component I set up a test that starts a burst that crosses the 4k boundary. This did not cause any error. Is that a check that should be active?
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When importing packages using the syntax `import package_name::*`, HDL_Linter outputs error `vlog-13006`, for instance: `Error: ./projects/axi/axi4_lite_subordinate.sv(4): (vlog-13006) Could not find …
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Can we add a user-defined property to enable the specification of the cpuif type from the SystemRDL code as well as from the command line? This would also make it easier to implement in a development …
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched the [documentation](https://chipyard.readthedocs.io/)
### Fe…