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First let me thank you for putting together this very nice solution for developing on DE10* platforms.
I have some issues that I'll split into separate github issues to keep track.
The first one…
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Hi
I have a trained DNN which weight is extracted on a .h5 file. What's the road map in order to implement this DNN on a FPGA?
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How much work is needed to convert this to support the DE0-Nano-Soc?
Also, would it be possible to add a Discussion tab, to this repo? I have some questions, including this one, which are not rel…
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Hi Seb,
Thanks for all the great work you've done. I'm wondering about the device tree source file that you've written. The FPGA configuration that I'm using will not enable some of the peripheral…
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Hi,
I am trying to use OpenCL SDK 17.1 (Quartus Standard ) with De1SoC
I am having a couple of problems
OS Ubuntu
Intel SDK installation
Quartus Prime Lite 17.1
Intel FPGA SDK for OpenCL 1…
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Hello everyone,
I am interested in creating a SoC with 2 cores and a custom communication between them (UART or something else). But reading the BaseSoC implementation, I see no trick that I could …
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Are there any examples of programming an OrangeCrab using the soft RISC-V core, but with custom "gateware" for hardware accelerated peripherals? My goal is to largely program using C/assembly, but to …
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It seems current open source FPGA dev tool kits are a bit long winded to setup and coming from a Linux sysadmin / devops background the aim would be to have all build environments use docker container…
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Hai @doonny , I have run inference on De1-SoC board with VEC_SIZE=8 and LANE_NUM=8 (other parameters remain unchanged).
However, the **Total kernel runtime** is 236.344 ms instead of 149.988 ms giv…
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Hi
I attempted to compile Pulpissimo on ZCU104. It ends up with timing constraints aren't met:
Current Timing Summary | WNS=-7.567 | TNS=-29782.275
The procedure I followed is:
1. download pulpis…