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### Version
Yosys 0.41+24 (git sha1 75f01ccee, g++ 8.3.0-6 -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
**Problem**
Usage of wired-or (wor) connections can result in …
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nextpnr-ice40 operates at the logic cell (LUT+FF) level. Investigate the effect of clustering related logic together to take advantage of any local feedback paths (are there any?) and to reduce the pl…
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LUTs in a tile can be cascaded together into a chain, useful for making a shift register style thing.
From http://www.clifford.at/icestorm/logic_tile.html
> Each LUT i has four input wires lutff_i…
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Probably dependent on https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/325
From http://www.clifford.at/icestorm/logic_tile.html
> Input lutff_i/in_3 can be configured to be dri…
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This has been an issue I've discussed with @eddiehung for a while, but I want to file it publicly so people can submit testcases for us to work through.
Essentially, the problem is that ABC9 - whic…
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Need at least an `alwayslink=True` on the kernel link target and pointing somewhere else as the `YOSYS_DATDIR` in the defines. Been using out-of-tree binaries thus far, but we should be able to resolv…
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We want to eventually port this to run natively on the MEGA65 for flashing the MEGA65 keyboard Lattice CPLD.
I assume LLVM-MOS will be the compiler of choice, since we need C++
It needs to support…
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```
ctx.addClock("clk_out_a", 100)
ctx.addClock("clk_out_b", 12)
```
```
nextpnr-ice40 --pre-pack clocks.py
```
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Convert input/output data storage from registers to block RAM.
We're currently using about 700 bits worth of shift registers... Maybe we can squeeze some more compute power out of certain devices b…
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hi,
who is managing this project?
I am looking for introduction to perceptrons and or neural nets using verilog.
and enjoy ice40 opensource tools see my tutorials for verilog on ice40: https:/…
peepo updated
5 years ago