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# Bug Report
## One-Line Summary
When using a `with` statement with multiple items, the behavior is incorrect.
## Issue Details
### Steps to Reproduce
```python
from artiq.experiment i…
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Hi
I am using xc7z020clg400-2 with Marvell Alaska 88e1512 phy chip. I took the nexys video design as reference. For reception( PC to board) it is working fine. But when transmitting from board to …
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**Issue by [whitequark](https://github.com/whitequark)**
_Friday Dec 14, 2018 at 17:40 GMT_
_Originally opened as https://github.com/m-labs/nmigen/issues/4_
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```
17:30 < sb0> whitequark: for m…
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# Bug Report
## One-Line Summary
I tried to put some function names in a `list` and let the kernel to call those functions by traversing this `list`. And get some weird behavior.
## I…
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For this version, would it be possible to change the bus width size of mem_nasti interface with the memory controller from 64 to 128 bits?
For instance, changing 64 to 128 below:
```
…
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I’m not sure if it’s a real GHDL issue or a VHDL language issue...
The below listed code is a short and hopefully typo free minimal example for one of our PoC arithmetic entities. These entities have…
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Hey, I want to build litex project with ethernet peripheral. I succesfully builded project and generated bit file. I'm trying to loading boot.json file but I got this error.
![image](https://github.…
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I am attempting to get the CVA6 APU running on a KC705 board.
What I have done so far:
- Cloned the CVA6 repository, installed the tools and successfully ran smoke-tests.sh
- Ran $make fpga BOA…
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Hello,
First of all thank you for this great repo.
I am trying to port this project to the UltraZed-EV card. For this I plan to use the SFP interface, since the RJ-45 connector goes to the PS pa…
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I download the RIFFA bitstream with Gen 2.0x8 configuration into my KC705 FPGA and installed the drivers on Ubuntu 18.04, and C test worked fine with the measured bandwidth of:
send bw: 3335.055111…