-
**Describe the bug**
The code below raises an error but is valid according to the LMR
**To Reproduce**
```systemverilog
class test;
bit [31:0] pattern;
constraint pattern_c {
fore…
-
I'm not sure if this is where to post this, however In the Programming FPGAs book in Chapter 4 on page 57 "A Counter in Verilog", the Constraints file for the Papilio is listed with the highlighted ch…
-
Hi,
I has been using your vim plug for a while, and it the best so far.
However, when I have a class with extern functions/tasks, the folding will not work expecting from the extern methods with ar…
-
This is a proposal for discussion.
The idea is to switch the linter from Verilator to Veriable.
https://github.com/chipsalliance/verible
Rationale
In addition to a command line lint, Verible…
zapta updated
6 months ago
-
Objective: bringing back the non-free model user experience, as an optional extension to QUCS.
on the QUCS end
- [x] implement dynamic loader (dlopen)
- [x] implement a dictionary for components
…
-
### Version
Yosys 0.45+106
### On which OS did this happen?
Linux
### Reproduction Steps
See attached archive. It contains the input verilog file, the Makefile, and the log of last Yosys run.
Ju…
-
Hi,
Does the write_verilog command in openroad have a switch for keeping hierarchy in a netlist? I used the read_verilog command in openroad to read a top level netlist file that instantiates two mod…
-
Please forgive me if this has already been issued. I'm kinda new to this project, and is working on a Verilog (instead of VHDL) version of the Time Card's FPGA codebase.
In the current open-source…
-
Subscribe to this issue and stay notified about new [daily trending repos in Verilog](https://github.com/trending/verilog?since=daily)!
-
Normally we have two terminals for a capacitor, but why we have an additional terminal called 'qin' in your Verilog-A file? Thank you for your help!