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Would be great if this repo can be updated with images that are synced with priv-1.10 version of the Rocket Chip and riscv-tools (e.g. https://github.com/freechipsproject/rocket-chip/commit/86c10b3cef…
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I followed the 3.1) Project Setup of the README.md.
After typing "make project" in the directory of /fpga-zynq/zedboard,I encountered one error.
The log information is here:
root@vm:/home/chang/f…
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**Issue by [jpmoniz](https://github.com/jpmoniz)**
_Tue May 12 11:32:12 2015_
_Originally opened as https://github.com/machinekit/machinekit/issues/631_
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Opening issue to capture work focused t…
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Dear doonny,
I'm trying to test PipeCNN framework on some Xilinx's FPGA embedded boards for take some power measurement. Actually I would like to compile the framework for Digilent ZedBoard but the s…
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Hi
I am running the pulpino on the ZedBoard and I wonder, if there is any possibility to debug the core? I successfully simulated my changes in the design with ModelSim and executed a sample program,…
bnkla updated
6 years ago
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I tried to compile by specifying platform to microzed. But several errors came out like:
`This design requires 28666 of such cell types but only 17600 compatible sites are available in the target …
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* stream sink
* ignored EOP
* request burst transfer via DMAC | PRI
Refer to ARM DDI 0424D.
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Hi,
I do not have zedboard or zybo. I have a board from xilinx with Zynq SoC.
Adding the new board does not seem to be trivial. There are several errors. I have one posted in another thread unde…
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I want to implement timer interrupt.
After I use `asm volatile("li t0,0x08\n" "csrrs zero,mstatus,t0\n")`,I successfully create the executable file.
But when I run it with `spike pk` ,the termin…
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Hi all, after I build the FPGA bitstream with the default project, I always got Timing constraints are not met. Is there any possible solution to this issue?