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Tried to build a simulation project with ipbb v0.5.0 , ipbus v1.4 and Questasim 10.7c
building FLI object file fails:
```(ipbb) -bash-4.2$ ipbb sim fli
/users/phdgc/DUNE/firmware/zcu102/zcu102/…
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I am getting unisim library related error. I have compiled Xilinx IPs for Questasim. Still, compilation giving an error. What could be the solution for this?
![Capture](https://user-images.githubuser…
dsp20 updated
5 years ago
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I am referring this example for compiling Xilinx IPs from Vunit environment [(https://github.com/VUnit/vunit/tree/master/examples/vhdl/vivado). But I am getting simulator related error. I am using Que…
dsp20 updated
5 years ago
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Hello,
I am a new user of vunit and was trying to run the 'VHDL user guide' example provided with Questasim and Python 3.4/2.7.
However I get the above error after successful compilation. It se…
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I am working on setting up TravisCI and possibly exploring the option of other CI environments as well. However, I am completely new to this and do not know how to accomplish this for an open source V…
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Attempting to run VRM using
```sh
vrun
```
Fails with
```
/opt/mentor/questa/2019.1/questasim/bin/../linux_x86_64/vrun: error while loading shared libraries: libX11.so.6: cannot open share…
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With reference to changes in New YAML based regression flow #46, these are my observations:
1. README.md still uses -tool irun instead of ius for the new flow
2. Also suggest adding "run.py --h…
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I'm currently evaluating PULPissimo platform with Ibex core and I encountered some strange behaviour with interrupts. It seems that after hitting breakpoint `mie` in `mstatus` register is reset to 0.
…
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Hi all,
I am facing the following Error message:
Cocotb initialisation failed - exiting
This appears here in the log of my test:
Loading /home/bpe/digflow_repo/digital_flow/trunk/verif/cocotb/bu…
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Hi,
I changed the INSTR_RDATA_WIDTH parameter from 128 to 32, since with 128 bits, the synthesis tool gets stuck in elaboration phase. However, when I try to re-run the helloworld code, the testbenc…