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I am trying to move ara on VCS, but met too many errors, and they are hard to fix.
Do you have the correct Compilation Options on VCS or irun? Or a script of running by VCS?
These are examples of…
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This is a tracking issue for the first steps towards implementing a hardware description language for Tydi types.
Currently the Tydi crate provides modules with the logical and physical stream type…
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Hi Patrick,
I see lots of code. However, I think we might want to agree on naming methodology as it would be nice if all were the same.
I would like something that is obvious - even to people wh…
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From the documentation:
```hs
-- | Test a protocol against a pure model implementation. Circuit under test will
-- be arbitrarily stalled on the left hand and right hand side and tested for
-- a n…
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Submitted by @Paebbels via Gitter:
in AXI4 Transmitter, please change
`Alert(ModelID, "Unimplemented Transaction: " & to_string(TransRec.Operation), FAILURE) ;`
to denote an operation like GET|CHE…
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Hello, I'm using the` Alveo accelerator boards U200`. I package the kernel as xclbin,use the interface `hls:: stream`. Can PYNQ interact with this interface?
sush as:
``` c++
void myproject(
h…
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There is a desire to have a generic stream abstraction in `nmigen.lib` which can be used / presented by the `nmigen-stdio` cores (among others). This issue exists to capture discussion around the desi…
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Hi,
In the axis_adapter module, if the `S_KEEP_ENABLE` parameter is disabled, the tkeep input signal should be taken as 1'b1. This was the case in the previous version of the module. In the current v…
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**For Vivado questions, please use [Vivado forum](
https://forums.xilinx.com/t5/Vivado-RTL-Development/ct-p/DESIGN)**
**For Vitis questions, please use [the Vitis forum](
https://forums.xilinx.co…
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**Describe the bug**
When using the AXI-Lite top-level interface, Vivado 2023.2 produces critical warnings like this for the AXI Stream interfaces for SLINK:
[BD 41-967] AXI interface pin /process…