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When I use vivado to synthesis the generated verilog,the command report an error:"module 'system' not found",the error is located at line 139 in rocketchip_wrapper.v.Is there any wrong?Or it lacks som…
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Hi,
I have integrated the L2 cache into the rocketchip provided by chipsalliance, and I would like to run a cache flush, but I do not know how to invoke this, would anyone have any related .asm sh…
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When I change CoreMark for RISCV(spike or Rocketchip), I also find gettime() always return 0 (start_time() and stop_time() always return -1) . I think it may some problems of clock in emulator. Could …
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I am trying to implement rocket chip on zedboard. I have given rocket chip and testchipip's paths in ..common/Makefrag. Also, I have initialized the submodules. When I run the command 'make project' i…
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I have completed the rocket-chip installation. But which verilog files or files will I use when synthesizing FPGA in vivado.I used freechips.rocketchip.system.DefaultFPGAConfig.behav_srams.v
freechip…
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`WithSbusNoC` :
why `serial-tl` maps to `fbus` in inNodeMapping, and no `cbus` mapping in outNodeMapping.
`Gemmini10ReRoCCOrigNoCConfig` :
the outNodeMapping has four `system[0-3]`, but `WithNBank…
FDH21 updated
10 months ago
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**Type of issue**: other enhancement
**Impact**: API modification
**Development Phase**: proposal
refactor freechips.rocketchip.diplomacy to move remaining old diplomacy helpers out to other…
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This issue tracks the TAC formally deciding which projects are capital "P" projects and which are incubation projects.
Updated **May 14, 2024**
| Project | Current Status | Proceed With LLC? |
…
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**Type of issue**: bug report
**Impact**: unknown
**Development Phase**: request
**Other information**
I want to generate mem tarce using the script `tracegen.py`. But I c…
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Hi,
I am trying litex to generate a rocket based soc for terrasic de2 115.
Command i used to build is:
`litex-boards/litex_boards/targets/terasic_de2_115.py --build --cpu-type rocket --cpu-va…