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os is win10
sbt 1.7.3
scala 2.12.18
java 11.0.19
SpinalHdl is 1.10.1
First, I compiled and run SpinalTemplateSbt at the PC connecting to Internet. It's OK.
```
[Runtime] SpinalHDL v1.10.1 …
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Hi,
I am getting following error when trying to build hdlConvertor using setup.py
command - python3 setup.py install --prefix /tmp/python_install/ --build-type Debug -- -DANTLR_JAR_LOCATION=/home/…
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## Describe the bug
`ot/verilog/verilog.cpp` cannot process my verilog demo file...
## To Reproduce
This is my verilog file generated by yosys, which is an inverter:
**./output/inverter.v*…
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This is a tracking issue for an effort to switch Calyx's testbenching.
## Background
Currently, all Calyx-compiled Verilog programs use the same [standalone testbench](https://github.com/calyxir/…
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This issue is about divergent behavior between `icarus-verilog`, `verilator`, and the Calyx interpreter.
Here's a toy eDSL program and it's associated data file:
```
# bug.py
import calyx.builde…
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As described in this blog post, GitHub Actions are transitioning from Node16 to Node20:
https://github.blog/changelog/2023-09-22-github-actions-transitioning-from-node-16-to-node-20/
All of the CI…
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Hi there,
Currently I am trying to synthesize PICORV32 onto DE0 Nano FPGA using Quartus Prime Lite.
I have no problem synthesizing with [synth_area_top.v](https://github.com/YosysHQ/picorv32/blo…
YapWC updated
1 month ago
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Error detected while processing /home/bhargavrajp/.vimrc[3]../home/utils/vim-9.0.0630/share/vim/vim90/syntax/syntax.vim[43]..BufRead Autocommands for "*.sv"..FileType Autocommands for "*"..Syntax Auto…
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Unsure if this actually applies to the project, as it probably doesn't come up in most (any?) netlists, but Verilog has the concept of primitives, both builtin (`XOR`, `AND`, etc), and [user generated…
agg23 updated
8 months ago
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#### Expected Behaviour
We should have no compiler warnings.
#### Current Behaviour
Some warnings in vqm2blif:
[ 50%] [BISON][VqmParser] Building parser with bison 3.8.2
/home/runner/work/vtr…