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signal-name-style - Does not like the word 'sample' as a variable name.
Code compiles on 2x EDA simulators.
Seem to only affect this rule, disabling rule works around the issue.
The followi…
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The following example compiles without errors / warnings and does not wrap the used out-of-range constant:
```haskell
module Test where
import Clash.Prelude
topEntity :: Signal System (Unsig…
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```
========================================================================================= FAILURES ==========================================================================================
____…
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### Is there an existing issue for this?
- [X] I have searched the existing issues
### Describe the bug
A subcircuit in verilog HDL made the browser stuck in loading without any responses for abou…
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Logisim cannot play nicely with other formats for describing circuits. It should support exporting and importing Verilog or VHDL code, using comments to annotate placement of components.
There's alre…
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**_chipyard release: 1.4.0_**
Hello,
I am running the following command to build the simulator:
```
make CONFIG=L1ScratchpadRocketConfig
```
then executing an `rv64ui-p-add` test on the built …
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I have some vague notion that it was once possible to set a user defined time resolution from the command line.
Was the option removed or was it never present?
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I think it would be a good idea to add a few tests (one specifically for `sqrt`) for the icarus-verilog backend. Perhaps benchmarks as well? This would require some additions to the Github Actions.
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I have recently started working with `cocotb-test`, trying to get away from the `makefile` method. It's amazing!
**plus_args:**
My understanding of `plus_args` usage (`PLUSARGS` in cocotb) is a …
-
When attempting bus definitions like this:
```
input [0:4] in ;
```
I get an error like this:
```
|
6 | input [0:4] in ;
| ^ expected identifier
```
How should I define a bus t…