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In order to create native application and be able to simulate in in both HW and software Vitis platform for our board needs to be created. Xilinx doesn't support our box out of the box, Vivado also do…
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Bumping to Xilinx Vivado2023.2 in our current container environment is failing with a couple of errors.
**Desktop:**
- OS: ESP centos7-full docker image
- CAD tools versions: Xilinx Vivado 2023…
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Path to the Tutorial: Vitis-Tutorials/Hardware_Acceleration/Feature_Tutorials/01-rtl_kernel_workflow
Hi everyone, I am new to Vitis RTL Kernel and want to develop my project base on this tutoria…
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Hi I am working on FPGA Nexys4 A7-100T and 35T .
There are two errors when I generate ibex bitstreamfile.
No matter which Nexys FPGA board I choose, I will receive the same error message.
Here ar…
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Hola! Tenemos una duda. Nuestro assembler está listo porque ya pasó todos los test cases de SuSsembler, además en Vivado no tenemos Critical Errors o errores, pero cuando conectamos la placa, generamo…
mrtti updated
1 month ago
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I am having trouble adding native FIFO xci IP generated in Vivado 2021.2.
Conflict seems to arise from the cl_axi_interconnect (shipped with Shell) which uses fifo_generator_v13_2_1(probably from p…
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Hola, soy del Grupo 59. Estoy revisando nuestro assembler de la E2 para la recorrección y me he dado cuenta que pareciera ser que tanto PUSH como POP meten o sacan datos en el stack _antes_ de cambiar…
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https://github.com/CTSRD-CHERI/cheribuild/blob/36d5dba8e3a9ae67a428eb7469309b19edefdae8/vcu118-run.py#L126
Is this the canonical way to check for something - I have my vivado aliased to vivado_lab,…
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Hola! Para contextualizar subo una imagen con un ejemplo en el enunciado de la etapa 2 que usa un arreglo.
![WhatsApp Image 2024-11-02 at 15 24 31](https://github.com/user-attachments/assets/056a550…
mrtti updated
3 weeks ago
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Hi,
I wanted to replicate a Litex soc with a Vivado block design. I was wondering if there is any way to generate a UartLite module without anything else included since the Litex UartLite control r…