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SB_GB_IO has a much lower (and completely predictable!) delay than SB_IO + SB_GB pair we are using now. In fact, using the latter pair has been observed to (rarely) lead to selftest failures due to se…
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**Issue by [Wren6991](https://github.com/Wren6991)**
_Sunday Mar 03, 2019 at 15:56 GMT_
_Originally opened as https://github.com/m-labs/nmigen/pull/38_
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The AsyncFIFO class is subtly different …
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## Actual Behavior
The following Verilog module:
```
William@William-THINK MINGW64 ~/src/tinyfpga-soc
$ cat pll-crash/build/top.v
/* Machine-generated using Migen */
module top(
inp…
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My intention with creating this issue is collecting/sharing information and gauging interest about running Linux on VecRiscv. From what I know, VexRiscv is still missing functionality, and it won't wo…
ghost updated
5 years ago
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The ICE40 toolchain has the ability to patch block ram in the emitted bitstream. However, because it uses heuristics to locate the memory, it requires that the ram contain random data.
It is possi…
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Well, if somebody have a branch with support of the latest Migen, please put a note here.
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```
./build/nexys_video_net_lm32/output.20180828-035725.log
---------------------------------------------
Traceback (most recent call last):
File "./make.py", line 143, in
main()
File "…
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## Steps to reproduce the issue
When creating code in migen for use with Vivado, the code is generated with custom attributes and then constraints applied in the XDC output.
The created Verilog …
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@gkasprow would it be possible to add the same WR circuitry to the RTM that we have on the AMC? My long term aim it to be able to generate a high-stability DAC clock from the WR clock (via the AMC FPG…
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As given in docs i am not able to understand how to link to iverilog and simulate it further in gtkwave.
I am not able to understand "make" commands in docs