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**Type of issue**: bug report
**Impact**: unknown
**Development Phase**: request
**Other information**
Since commit aa459e01, some 83 additional 'auto_tile_master_*' wire…
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Include the Vivado project for the Zedboard in the final release of v2.0.
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Over the past couple of years, we've developed firmware entities that allow one to read & write lists of IPbus transactions over PCIe - i.e. a PCIe transport layer interface for the IPbus transactor. …
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I followed the flow given in [sifive/duh/README.md](https://github.com/sifive/duh/blob/master/README.md) on [sifive/demo-block/rtl/pio.v](https://github.com/sifive/demo-block/blob/master/rtl/pio.v) to…
ghost updated
5 years ago
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`Axi4.burst.INCR` shall align the address [1], A3-49 in `Axi4.incr`, how is this maintain?
I'm new to _SpinalHDL_ and currently aiming to port some `Axi4` implementation to [migen-axi](https://githu…
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SV Interface 導入に伴い、未実装状態になっているので、AXI4 Lite 用のモジュールを実装する。
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I have a question about mem AXI port addressing.
The /subsystem/Configs.scala defines the mem and mmio port addresses.
The original setting of mem is:
class WithDefaultMemPort extends Config((si…
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@max-ruttenberg pointed this out
Is there any reason we shouldn't do this for cosimulation? Has anyone seen this cause issues?
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If a PE has local memories (or more than one slave interface, for that matter), DSE will still try to build more instances than will fit in the current 128 slots limit. There are several possible solu…
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OS: Ubuntu
Tool Version: Vivado HLS 2018.2
I am getting this error:
`ERROR: [SYNCHK 200-22] ../xfopencv/include/common/xf_utility.h:370: memory copy is not supported unless used on bus interface …