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Hello!
I'm working on a design where I will be receiving data in the PL and I'm using a DMA to pass it to the PS. The DMA only has the write channel activated. This is my Vivado design:
![image]…
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I'm building a shell on VC707 (not _sifive/freedom_ repo). My system works well when the address map can be represented in 32-bit.
![image](https://user-images.githubusercontent.com/25481041/9940221…
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There is Xilinx IP that checks for violations of the AXI protocol on a bus: https://www.xilinx.com/products/intellectual-property/axi_protocol_checker.html
When designing a HDL core through SNAP it…
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It feels like it could be useful to allow for the passing in of cells that contain `ref`s to other components that also take in `ref` cells. Currently, there isn't a way to express this in the languag…
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Hello, I found that the "priority_encoder" was optimized out when synthesizing "axi_interconnect" using Vivado. Do you know the reason behind this?
The following image shows the synthesis schematic …
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[AXI总结.pdf](https://github.com/xmxn3559/doc/files/2205006/AXI.pdf)
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Hi Alex,
Thanks for sharing your verilog-pcie library! I have been running simulations for the various components and examples as well as studying the source but still have a few questions. For all…
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Hi,
I test the hardware algorithm in 4.14.0-xilinx, and compare with software algorithm.
By the following result, I thik that AXI communication consume too much cycles.
Maybe reduce them, especiall…
55-AA updated
4 years ago
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Thanks for the nice tutorial!! Would it be possible to add the `axi_gpio_switches_leds.overlay` that enables the AXI GPIO controller IP core(s) in the design?
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![image](https://user-images.githubusercontent.com/37424070/99603667-a1c9a480-29b8-11eb-814c-025cc096fc14.png)