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This is a proposal for a new testers API, and supersedes issues #551 and #547. Nothing is currently set in stone, and feedback from the general Chisel community is desired. So please give it a read an…
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Hello,
I want to monitor a Axi bus inside the module, and it drives by a clock that is different from the input clock.
```scala
val perpPort = dut.socInst.logicMainInst.coreInst.io.d_perp // An AXI…
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Using GHDL from git:
```sh
$ ghdl --version
GHDL 4.0.0-dev (3.0.0.r714.gf171833e7) [Dunoon edition]
Compiled with GNAT Version: 10.5.0
static elaboration, mcode code generator
Written by Trist…
jeras updated
11 months ago
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[Rule 5](https://github.com/VUnit/vunit/blob/master/vunit/vhdl/verification_components/src/axi_stream_protocol_checker.vhd#L115) of the AXI stream protocol checker ensures that `tdata` is valid when `…
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I am running 2 Verilated sims under Verilator 5.021 on Ubuntu (22.04.3). The first one is a fairly small standalone one and the VCD is generated and loads fine into gtkwave. The second one is more …
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# Explanation and question
How does the `byte_endianness` work with regards to the `t_axistream_bfm_config` and its associated VVCs?
It seems to have no effect on the output and input of the VVCs wh…
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Hi,
I have to connect my design with ARM processor and I have to create 2 AFIs with the same design. One is transmitter and another is receiver. But both have to be configured in a different way so…
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Hey Guys,
I worked with hls4ml the past few months and now I finally wanted to deploy a model I transformed with hls4ml, but I dont really know how I have to initialize my IP core created with hls4…
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我已经仔细检查了硬件连线，vitis软件的中断部分也仔细和我的板子的中断例程进行了对比，还是接收不到apdone的中断，摄像头已经有显示了，请问您有什么意见吗，accel_conv的ip还需要在vivado中进行什么设置吗，引脚定义之类的？
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In a very custom version of the processor I am (_mis_)using the [Smcsrind](https://github.com/riscv/riscv-indirect-csr-access) ISA extension to add further CPU-local hardware accelerators. Even though…